Hot Chips 2026 will be held Sunday, August 23 - Tuesday, August 25, 2026 at Memorial Auditorium, Stanford, Palo Alto, CA.
Early registration is now open; register by Friday, July 31, 2026, for the best rate.
Advance Program
Tutorials: Sunday, August 23rd, 2026
| Title | Affiliation |
|---|---|
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Breakfast/registration |
|
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Tutorial 1: Memory technology Chair: Suresh Rajgopal |
|
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Introduction |
Objective Analysis |
|
HBM Architecture |
Micron |
|
HBM Base Die |
Samsung |
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HBM Packaging |
SK Hynix |
|
Break |
|
|
Tutorial 1: Memory technology (cont) |
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|
3D Memory |
D-Matrix |
|
Flash (HBF) in AI Compute |
Oxmiq Labs |
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Lunch |
|
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Tutorial 2: RISC-V Chair: Marcel Tromp |
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Update on RISC-V standards and adoption, including profiles and platforms |
SiFive |
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Evolution of enterprise open-source on RISC-V and architectural convergence on RVA23 |
Canonical |
|
Break |
|
|
Tutorial 1: RISC-V (cont) |
|
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RISC-V profile and platform for interoperability with NVIDIA GPUs |
NVIDIA |
|
RISC-V for automotive: opportunities and challenges |
Infineon |
|
Reception |
Conference Day 1: Monday, August 24th, 2026
| Title | Affiliation |
|---|---|
|
Breakfast/registration |
|
|
Welcome |
|
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Session: CPU 1 Chair: Ian Bratt |
|
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The future IBM Z & LinuxONE Processor and AI Inference Acceleration Chipset |
IBM |
|
Intel Core Series 3, codename Wildcat Lake |
Intel |
|
NVIDIA Vera |
NVIDIA |
|
Break |
|
|
Session: CPU 2 Chair: Gabriel Southern |
|
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Next-Generation Arm-based CPU FUJITSU-MONAKA for green AI data center |
Fujitsu |
|
Arm AGI : A Disaggregated, Chiplet-Based Server SoC for scalable coherency and memory Bandwidth in the Terabyte/s Era |
Arm |
|
Diamond Rapids: Next Generation Intel Xeon CPU |
Intel |
|
Lunch |
|
|
Keynote 1 Chair: Borivoje Nikolic |
|
|
Keynote announcement coming soon |
|
|
Session: Automotive Chair: Yasuo Ishii |
|
|
Eagle-N: Chiplet-Based SoC for Scalable Automotive AI |
BOS Semiconductors |
|
Waymo sensor processing and AI inference accelerator |
Waymo |
|
Break |
|
|
Session: GPU Chair: Pradeep Dubey |
|
|
NVIDIA Rubin GPU: Driving the Era of Agentic AI |
NVIDIA |
|
AMD Instinct MI400 Series GPU Architecture |
AMD |
|
System Architecture of the AMD MI400 Series GPU |
AMD |
|
Crescent Island: GPU Designed for Agentic AI Inference |
Intel |
|
TCMM Awards |
|
|
TCMM Awards |
|
|
Reception |
Conference Day 2: Tuesday, August 25th, 2026
| Title | Affiliation |
|---|---|
|
Breakfast/registration |
|
|
Session: FPGA Chair: Thierry Tambe |
|
|
AMD Industry 1st Adaptive SoC/FPGA with PQC |
AMD |
|
Versal RF |
AMD |
|
Session: Memory Chair: Jae W. Lee |
|
|
Samsung LPDDR5X-PIM with In-memory Processing |
Samsung |
|
XCENA MX1 CXL Computational Memory Device |
XCENA |
|
Break |
|
|
Session: Networking & Interconnect Chair: Greg Papadopoulos |
|
|
Thor Ultra: An Ethernet NIC Chip Optimized for AI & HPC |
Broadcom |
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NVIDIA Spectrum-X Multiplane Network Architecture |
NVIDIA |
|
Massively Parallel Optical I/O Powered by Ultra-High-Density Micro-LEDs |
Mojo Vision |
|
NVIDIA BlueField-4 Processor Powers the AI Factory Operating System |
NVIDIA |
|
Lunch |
|
|
Keynote 2 Chair: Cliff Young |
|
|
Keynote announcement coming soon |
|
|
Session: AI 1 Chair: Sherry Xu |
|
|
MTIA 400: Architecture for GenAI + Recommendation Systems, Training |
Meta |
|
Break |
|
|
Session: AI 2 Chair: John Wright |
|
|
LPX: A Heterogeneous GPU-LPU |
NVIDIA |
|
The Cerebras Rack-Scale Architecture for Wafer Scale Engine |
Cerebras |
|
MAIA 200: A Data Center Scale AI system - MAIA-200 Accelerator |
Microsoft |
|
Break |
|
|
Session: AI 3 Chair: Brucek Khailany |
|
|
Dataflow at Scale: the SN50 RDU |
SambaNova |
|
The Eighth Generation TPU Family: Two Chips Optimized for Training and Serving in the Agentic Era |
|
|
Vice-Chair closing remarks |
|
|
Vice-Chair closing remarks |
Posters
| Title | Affiliation |
|---|---|
| Croc: Training the Next Generation Chip Designers on Domain-Specific End-to-End Open Source Silicon | ETH Zurich |
| Gemmelos: A Dual-Chip Platform in Intel 16 for Multimodal Edge AI Applications | UC Berkeley |
| Pistil: A 16-nm Accelerator Co-Designed with a 20-Chiplet 2.5D System-in-Package Architecture for Distributed Small Language Model Inference at the Edge | Harvard |
| Tensor Processing with Large-scale Homodyne Photonic Crossbar | Opticore |
| From Python to Silicon: First Tapeouts Produced by an End-to-End Open-Source Hardware Compiler | PNNL |
| ETHEREAL: a 17µs-latency event-driven GNN processor for high-resolution edge-AI vision | KU Leaven |
| LUTs and Bolts: eFPGA SoC with Hardened MVM Engine for Deep Learning in 28nm | CMU |
| HiVec: Scalable and Energy Efficient CGRA in a RISC-V SoC for Wearables | A*STAR |
| CN101 - Thermodynamic Computing for Generative AI in Digital CMOS | Normal Computing |
| From Microarchitecture to Silicon: An End-to-End RISC-V CPU Design Course | University of Tokyo |
| A Low-Power and Real-Time Vision-Language Navigation Processor with 3D Spatial Reasoning for Embodied Agents | KAIST |