Hot Chips 2026 will be held Sunday, August 23 - Tuesday, August 25, 2026 at Memorial Auditorium, Stanford, Palo Alto, CA.
Early registration is now open; register by Friday, July 31, 2026, for the best rate.
Advance Program
Tutorials: Sunday, August 23rd, 2026
| Time (PDT) | Title | Presenters |
|---|---|---|
| 8:00AM-9:00AM |
Breakfast/registration |
|
| 9:00AM-11:00AM |
Tutorial 1: Memory technology Chair: Suresh Rajgopal |
|
|
Memory: Feeding AI’s voracious hunger for data |
Jim Handy, Objective Analysis | |
|
Evolving memory architectures for AI |
Raghu Sreeramaneni, Micron | |
|
HBM Base Die: How will HBM evolve in the future by utilizing the logic process? |
Sangwook Han, Samsung | |
|
Advanced packaging for High Bandwidth Memory (HBM) |
Jaesik Lee, SK Hynix | |
| 11:00AM-11:30AM |
Break |
|
| 11:30AM-12:30PM |
Tutorial 1: Memory technology (cont) |
|
|
3D DRAM based Accelerator for Generative Inference |
Sudeep Bhoja (D-Matrix) & Aayush Ankit (Meta) | |
|
HBF in AI Compute - A System Architect’s view |
Anurag Agrawal & Radhakrishna Giduthuri, Oxmiq Labs | |
| 12:30PM-1:45PM |
Lunch |
|
| 1:45PM-3:15PM |
Tutorial 2: RISC-V Chair: Marcel Tromp |
|
|
Update on RISC-V standards and adoption, including profiles and platforms |
Krste Asanovic, SiFive | |
|
Evolution of enterprise open-source on RISC-V and architectural convergence on RVA23 |
Gordan Markus, Canonical | |
| 3:15PM-3:45PM |
Break |
|
| 3:45PM-5:00PM |
Tutorial 1: RISC-V (cont) |
|
|
RISC-V profile and platform for interoperability with NVIDIA GPUs |
Frans Sijstermans, NVIDIA | |
|
RISC-V for automotive: opportunities and challenges |
Thomas Roecker, Infineon | |
| 5:00PM-7:00PM |
Reception |
Conference Day 1: Monday, August 24th, 2026
| Time (PDT) | Title | Presenters |
|---|---|---|
| 8:00AM-9:15AM |
Breakfast/registration |
|
| 9:15AM-9:30AM |
Welcome |
|
| 9:30AM-11:00AM |
Session: CPU 1 Chair: Ian Bratt |
|
|
The future IBM Z & LinuxONE Processor and AI Inference Acceleration Chipset |
Christian Zoellin, IBM | |
|
Intel Core Series 3, codename Wildcat Lake |
Lance Hacking, Intel | |
|
NVIDIA’s Vera CPU |
Jonathon Evans & Polychronis Xekalakis, NVIDIA | |
| 11:00AM-11:30AM |
Break |
|
| 11:30AM-1:00PM |
Session: CPU 2 Chair: Gabriel Southern |
|
|
Next-Generation Arm-based CPU FUJITSU-MONAKA for green AI data center |
Ryohei Okazaki, Fujitsu | |
|
Arm AGI : A Disaggregated, Chiplet-Based Server SoC for scalable coherency and memory Bandwidth in the Terabyte/s Era |
Deepak Goel, Arm | |
|
Diamond Rapids: Next Generation Intel Xeon CPU |
Akhilesh Kumar, Intel | |
| 1:00PM-2:15PM |
Lunch |
|
| 2:15PM-3:15PM |
Keynote Chair: Cliff Young |
|
|
Compute in Motion: Challenges of Autonomous Driving |
Daniel Rosenband, Waymo | |
| 3:15PM-4:15PM |
Session: Automotive Chair: Yasuo Ishii |
|
|
Eagle-N: Chiplet-Based SoC for Scalable Automotive AI |
KM Lim, BOS Semiconductors | |
|
Waymo sensor fusion processor |
Sabareesh Ravikumar, Waymo | |
| 4:15PM-4:45PM |
Break |
|
| 4:45PM-6:45PM |
Session: GPU Chair: Pradeep Dubey |
|
|
NVIDIA Rubin GPU: Driving the Era of Agentic AI |
Manas Mandal, Rajballav Dash & Ravi Manyam, NVIDIA | |
|
AMD Instinct MI400 Series GPU Architecture |
Vamsi Krishna Alla & Maiyuran Subramanian, AMD | |
|
System Architecture of the AMD MI400 Series GPU |
Steve Scott, David Riddoch & Krishna Doddapaneni, AMD | |
|
Crescent Island: GPU Designed for Agentic AI Inference |
Sumit Mohan & Hong Jiang, Intel | |
| 6:45PM-7:00PM |
TCMM Awards |
|
|
TCMM Awards |
Gabriel Southern | |
| 7:00PM-9:00PM |
Reception |
Conference Day 2: Tuesday, August 25th, 2026
| Time (PDT) | Title | Presenters |
|---|---|---|
| 7:45AM-8:30AM |
Breakfast/registration |
|
| 8:30AM-9:30AM |
Session: FPGA Chair: Thierry Tambe |
|
|
AMD Industry 1st Adaptive SoC/FPGA with PQC, Advanced Memory Features, and PCIe Connectivity |
Jaideep Dastidar & Thomas To, AMD | |
|
Versal RF |
Jeff Cuppett, AMD | |
| 9:30AM-10:30AM |
Session: Memory Chair: Jae W. Lee |
|
|
Samsung LPDDR5X-PIM with In-memory Processing |
Karam Hwang, Samsung | |
|
XCENA MX1 CXL Computational Memory Device |
Harry Kim (XCENA) & Jinin So (Samsung Electronics) | |
| 10:30AM-11:00AM |
Break |
|
| 11:00AM-1:00PM |
Session: Networking & Interconnect Chair: Greg Papadopoulos |
|
|
Thor Ultra: An Ethernet NIC Chip Optimized for AI & HPC |
Hemal Shah, Broadcom | |
|
NVIDIA BlueField-4 Processor Powers the AI Factory Operating System |
Moshe Anschel, NVIDIA | |
|
NVIDIA Spectrum-X Multiplane Network Architecture |
Gilad Shainer, NVIDIA | |
|
Massively Parallel Optical I/O Powered by Ultra-High-Density Micro-LEDs |
Mike Wiemer, Mojo Vision | |
| 1:00PM-2:15PM |
Lunch |
|
| 2:15PM-4:15PM |
Session: AI 1 Chair: Sherry Xu & John Wright |
|
|
MTIA 400: Architecture for GenAI + Recommendation Systems, Training |
Junqiang Lan, Meta | |
|
LPX: A Heterogeneous GPU-LPU |
Igor Arsovski & Santosh Raghavan, NVIDIA | |
|
The Cerebras Rack-Scale Architecture for Wafer Scale Engine |
Sean Lie, Cerebras | |
|
MAIA 200: A Data Center Scale AI system - MAIA-200 Accelerator |
Prashant Ranjan & Jackson Peng, Microsoft | |
| 4:15PM-4:45PM |
Break |
|
| 4:45PM-6:15PM |
Session: AI 2 Chair: Brucek Khailany |
|
|
Dataflow at Scale: the SN50 RDU |
Raghu Prabhakar, SambaNova | |
|
The Eighth Generation TPU Family: Two Chips Optimized for Training and Serving in the Agentic Era |
Norman Jouppi & Sridhar Lakshmanamurthy, Google | |
|
You Can Just Build |
Richard Ho, Ravi Narayanaswami & Chris Leary, OpenAI | |
| 6:15PM-6:20PM |
Vice-Chair closing remarks |
|
|
Vice-Chair closing remarks |
Nhon Quach |
Posters
| Title | Authors & Affiliation |
|---|---|
| Croc: Training the Next Generation Chip Designers on Domain-Specific End-to-End Open Source Silicon | Enrico Zelioli, Philippe Sauter, Thomas Benz, Hannah Pochert, Luisa Wüthrich, Beat Muheim, Frank Kagan Gürkaynak, and Luca Benini; ETH Zurich |
| Gemmelos: A Dual-Chip Platform in Intel 16 for Multimodal Edge AI Applications | Nicolas Rakela, Yash Kodali, Marie-Anne Xu, Alonso Zul Alonso, John Lomax, Jonathan Wang, Ethan Gao, Jasmine Angle, Sunjin Choi, Borivoje Nikolić, and Vikram Jain; UC Berkeley |
| Pistil: A 16-nm Accelerator Co-Designed with a 20-Chiplet 2.5D System-in-Package Architecture for Distributed Small Language Model Inference at the Edge | Nestor Cuevas, Matthew Adiletta, Haebin Do, Yun-Chen Lo, Kevin Kim, Jennifer Zhou, Kevin He, Alicia Golden, Isaac Leffler, Connor Ryan, Chris Green, Garrett Tan, Alexandra Forsythe, Nichole Murray, Lee Kimes, Rick Stevens, David Brooks, and Gu-Yeon Wei; Harvard |
| Tensor Processing with Large-scale Homodyne Photonic Crossbar | Lian Zhou, Yuan Li, Yun-Jhu Lee, Chun-Ho Lee, Kaiwen Xue, Kiwon Kwon, Weipeng Zhang, Songlin Zhao, Jason Moraes, Ryan Hamerly, Mengjie Yu, and Zaijun Chen; Opticore |
| From Python to Silicon: First Tapeouts Produced by an End-to-End Open-Source Hardware Compiler | Ankur Limaye, Nicolas Bohm Agostini, David Kong, Nrusinga Charan Gantayat, Gianmarco Accordi, Max Ramstad, Lakshmi Varshika Mirtinti, Vito Giovanni Castellana, Joseph Manzano, Jeff Jun Zhang, Gage Hills, and Antonino Tumeo; PNNL |
| ETHEREAL: a 17µs-latency event-driven GNN processor for high-resolution edge-AI vision | Adrian Kneip, Martin Lefebvre, Victoria Catalán Pastor, Daniel Gehrig, Davide Scaramuzza, Marian Verhelst, and Charlotte Frenkel; KU Leuven, TU Delft |
| LUTs and Bolts: eFPGA SoC with Hardened MVM Engine for Deep Learning in 28nm | Jason Cheung, Caroline Locke, Andrew Park, Surya Thenarasu, Larry Tang, James Hoe, Prashanth Mohan, and Ken Mai; CMU |
| HiVec: Scalable and Energy Efficient CGRA in a RISC-V SoC for Wearables | Rakshith Harish, Rohan Juneja, Pranav Dangi, Zhenyu Bai, Vishnu Nambiar, Yi Sheng Chong, Bin Zhao, Vishruti Ranjan, Rahul Dutta, Li-Shiuan Peh, Tulika Mitra, and Anh Tuan DO; A*STAR |
| CN101 - Thermodynamic Computing for Generative AI in Digital CMOS | Brandon Birchall, Lars Holdijk, Denis Melanson, Vincent Cheung, Nicholas Lehrter, Maxwell Aifer, Samuel Duffield, Jan Ernst, Saavan Patel, Antonio J. Martinez, Gavin Crooks, Patrick J. Coles, Zach Belateche, and Marc Bright; Normal Computing |
| From Microarchitecture to Silicon: An End-to-End RISC-V CPU Design Course | Junichiro Kadomoto, Tomoya Ota, Riki Onaga, Yuichi Matsuno, and Makoto Ikeda; University of Tokyo |
| A Low-Power and Real-Time Vision-Language Navigation Processor with 3D Spatial Reasoning for Embodied Agents | Seryeong Kim, Jongjun Park, Sangmyoung Lee, Hyungnam Joo, Wonhoon Park, Seokchan Song, Junha Ryu, Gwangtae Park, Sangjin Kim, Jiwon Choi, Seongyon Hong, Hyeonrae Kim, and Hoi-Jun Yoo; KAIST |