| Ailsa Sun |
Undergrad at UC Berkeley. Enjoys mathematics, post-si debugging, and staring at waveforms. Can’t digest silicon :(. |
| Alberto Gonzalez Trejo |
Research engineer and PhD candidate at the Barcelona Supercomputing Center - Universitat Politècnica de Catalunya |
| Amber Kahklen |
MEng in Electrical and Computer Engineering from Oregon State 2025. Focus on artificial intelligence and semiconductors, including machine learning, deep learning, semiconductor physics & fabrication. Additional coursework in HPC architecture, parallel programming, and joint SW/HW optimization. Strong interest in digital and semiconductor system design and machine learning in hardware design. Open to permanent opportunities. |
| Amir Iravani |
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| Anish Govind |
I am currently finishing a M.S. in Computer Engineering in the Electrical and Computer Engineering department at UCSD. I have experience in RTL design, physical design, and VLSI CAD. Enjoys building computers, playing basketball, and playing video games in my free time. |
| Arda Caliskan |
Second year PhD student in Computer Engineering at the University of Southern California, researching superconducting electronics. Experience taping out in Intel 16nm. Also interested in embedded firmware and RTL design. |
| Charitha Tumkur Siddalingaradhya |
I am a Master’s student in Computer Engineering at Virginia Tech . I am highly interested in RTL design and CPU microarchitecture, and I currently conduct research in the BEARHW Lab with Prof. Wenjie on hardware security. I have prior industry experience at Apple in Linux administration and networking, and at Maven Silicon in hardware design.. |
| Connor Lu |
Junior in EECS at UC Berkeley who’s interested in computer architecture. I have experience in research building EDA tools for physical design flows and digital design experience. Also, I enjoy building computers, tech, and custom hardware and software. |
| Evan Li |
Senior EECS @ UC Berkeley. Experience taping out mixed signal wireless chip and designing hyperscale data center ethernet switches for ML. Experience in frontend/backend methodology research. I am seeking opportunities in full-time digital design verification roles. |
| Francisco Gutierrez |
Masters Computer Engineering at UCSD. Graduating End of the Year. Experience in writing code in HPC and in managing supercomputers at SDSC. |
| James Lukas |
Graduating End of the Year Bachelors Electrical Engineering and Computer Science @ UC Berkeley. Experienced in robotics simulations and FPGA Bringup |
| Jessica Li |
EECS sophomore at UC Berkeley interested in computer architecture and power electronics. Prior experience in embedded systems with collegiate motorsport. Gaining ASIC/FPGA digital and analog design experience in the upcoming year |
| Jim Fang |
3rd-year Undergrad in EECS @ UC Berkeley. Interested in VLSI and emulation/simulation technologies. |
| Jonathan Ji |
I am currently a junior at UC Berkeley studying EECS. I am experienced in RISC-V architecture, PCB design/verification, and AVR firmware development. Outside of my studies, I enjoy getting my ankles broken in soccer, building harnesses at 3 AM, and watching silly orange cat videos. |
| Justin Yang |
I am a rising sophomore studying EECS at Berkeley. I’m interested in computer architecture and AI. Need internship pls anyone 🙏. |
| Karina Lelaisromant |
I’m Karina Lelaisromant, a Cybersecurity student at Las Positas College, graduating in December 2025. I hold the Cybersecurity Certification (CC) from ISC2 and am an active member of WiCyS, ISC2, and Cyberjutsu. I regularly volunteer in the cybersecurity community and am passionate about technology and problem-solving. I am eager to pursue internships, job opportunities, and challenges that help make the world a safer place. |
| Kelly Choate |
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| Kevin Gubbi |
Kevin Immanuel Gubbi is a 4th year Ph.D. candidate in Electrical and Computer Engineering at UC Davis focusing on hardware security, Applied Machine Learning, and EDA. He has industry experience at Samsung Austin Research Center (SARC/ACL) developing a reinforcement learning–based chip design optimization framework, and at AMD on power side-channel attack mitigation. His work bridges academic research and industry to advance secure and efficient semiconductor design. |
| Khai Vu |
Masters student of Computer Engineering at UC Davis finishing June 2026. I have experience in RTL design and verification for DSP applications, HPC applications and design and network programming for RDMA applications. Currently doing research in smartNIC offload |
| Luis Cardenas |
2nd year undergraduate (EECS) at UC Berkeley. I have experience with Robotics, Embedded Systems & Machine Learning and looking to branch off towards Computer Architecture. |
| Maheshwari Muddabasavaraju |
I am a Master’s student in Computer Engineering at Arizona State University, graduating in May 2026, with a focus on Embedded Systems. I have industry experience at Enphase Energy as an Embedded Test Intern and Associate Engineer, where I specialized in firmware testing, automation scripting, and cross-functional collaboration. My projects include developing custom processor branch predictors, optimizing cache replacement policies, and creating adaptive filtering algorithms for radar imaging at DRDO. I am passionate about designing efficient and reliable embedded systems that make a real-world impact. |
| Marie-Anne Xu |
Senior in EECS at UC Berkeley. I have research experience in FPGA design, teaching experience in computer architecture, and interests in operating systems and hyperscale datacenters. Gaining bringup and tapeout experience in the coming year; always looking for research and industry opportunities! |
| Nathan Carter |
Senior EECS student at UC Berkeley, (graduating Dec. 2025). Experienced in ASIC/FPGA Design & Verification. RISC-V architecture, and tapeout experience with a 2D Conv accelerator IP Block as part of a team effort to build a CNN ML chip. Seeking full-time roles for January 2026 |
| Prakhar Gupta |
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| Preetham Reddy Goudelly |
Master’s student in Electrical Engineering at ASU with specialized focus on high-speed I/O design and mixed-signal circuit development. Currently working as a Research Assistant, implementing a UCIe Express bus serializer, featuring 32:1 multiplexing architecture |
| Roshan Parekh |
Hi, I’m a senior at UC Berkeley interested in computer architecture, IC design, and HW/SW co-design. My experience includes designing and implementing a DMA engine for a DSP chip tapeout, conducting research on chiplets, currently focused on the implementation and verification of a UCIe digital stack, and, in my free time, I enjoy working on personal projects. |
| Samprithi Vilvasigamani |
I recently graduated with an M.S. in Electrical and Computer Engineering from the University of Illinois Chicago, with a focus on digital design and verification. My experience includes building UVM testbenches for RISC-V processors and AMBA protocols (APB, AHB, AXI), developing functional coverage models, and debugging protocol-level issues. I have designed and verified RTL for RISC-V processors, AXI4 interfaces, and custom IPs, and I enjoy bridging architecture with verification methodology. I am actively seeking opportunities in ASIC/SoC Design Verification and Digital Design |
| Shreesh Tripathi |
I love computer programming, architecture, design, and the underlying physics and math that make it all possible. I’m a graduate student at Carnegie Mellon University, majoring in Electrical and Computer Engineering. I’ve worked on problems like compute-in-memory and reconfigurable logic, and I’m currently interning with Nvidia’s GPU Fullchip verification team in Santa Clara. I’ll be out in the job market in January 2026, and I’d love to learn about the problems your team is working on. You can learn more about me here: https://shreesh.xyz/ |
| Venkateshwaran Sivaramakrishnan |
Pursuing M.S. in Computer Engineering (ECE) at UCSD, graduating in December 2025. Worked at Synopsys for 2 years as Senior ASIC Digital Design Engineer in design and verification of RISC-V processors. I have experience in RTL design, and verification infrastructure development. Big fan of all things tech. Research focused on Branch Predictors in Computer Architecture and ML in CAD. |
| Sonia Zhang |
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| Sushmitha Ayyanar |
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| Umer Shahid |
I am a Senior Engineer at 10xEngineers, RISC-V architecture specialist, and Lecturer at UET Lahore with over five years of experience in processor verification and compliance testing. I serve as Vice Chair of RISC-V International’s SIG-ARCH and Chair of the Certification Steering Committee Work Group on Tests & Model Recommendations, contributing to emerging ISA extensions and Architecture Compatibility Tests. My research, as part of my PhD, focuses on performance evaluation and enhancement of RISC-V SoCs using Gem5. |
| Yash Kodali |
I’m a rising senior studying Electrical Engineering and Computer Sciences at UC Berkeley, and have a strong interest in computer architecture and digital IC design. I have experience taping out and bringing up two digital chips (focused on ML and DSP applications). I also like to experiment with FGPAs and explore processors and emulation on the side. |
| Skylar Lo |
UCLA class of 2025, B.S. in Psychobiology. Passionate about finance and fitness |
| Andrew Sabot |
I am a PhD student at Harvard University and I will be defending at the end of August. My research has been on accelerating machine learning computations through scheduling and model training/ design. I am looking for full time roles. My thesis title is: Everything Is a Matrix: Minimizing Data Movement and Parameter Count Across the Machine Learning Stack |
| Ruhi Yusuf |
I’m studying Electrical Engineering at the University of Michigan, with interests in VLSI, PCB design, and photonics. My research includes developing low-noise photodetectors for quantum communication and working with photonic integrated circuits and FPGA-based control. Looking for stimulating internships and research opportunities in hardware, photonics, and circuit design! |
| Chloe Shen Yi Wong |
Hi, I’m Chloe - rising senior at UC Berkeley majoring in CS + DS. Interests are in low-level systems, ML and architecture, but always looking to explore new things! Experience includes embedded eng @ Annapurna, data sci @ Linkedin and ML/AI @ Dell. Outside of work I’m passionate about teaching (TA for comp arch!), art and dance. Looking for full time work and research opportunities in systems, arch, or anything similar. Let’s chat! |
| David Kong |
4th year PhD candidate at Harvard University researching emerging memory technologies and 3D integration techniques. Led 3 chip tapeouts during PhD so far (including compact modeling, analog design, layout, RTL, physical implementation & firmware). Previous industry experience designing SerDes, display backplanes, performance modeling and image sensor firmware. Looking for internships! |
| Alan Ma |
Undergrad in EE + CS @ Stanford with a fascination with the future of compute via accelerators. Researched neuromorphic systems at the Brains in Silicon Lab previously. Currently working on package design tools on the chip architecture team at d-Matrix. I love all things chips, the tortilla kind included! |